Embodiments of the invention concern a method and an apparatus for determining a minimum/maximum of a plurality of binary values, more specifically, embodiments of the invention concern a method and an apparatus for determining from a plurality of binary values stored at different locations remote from a central processor a minimum/maximum value.
Memory elements and integrated circuits (IC) need to be tested to ensure proper operation, and in particular, testing is a requirement during IC or memory development in manufacturing. During testing such devices under test (DUTs) are exposed to various types of stimulus signals, and responses from the devices are measured, processed, and usually compared to an expected response. Such testing may be carried out by automated test equipment (ATE) which usually performs these tasks according to a device-specific test program.
Examples for such automated test equipment are the Verigy V93000 Series and the Verigy V5000 Series, the first being a platform for testing system-on-a-chip, system-on-a-package, and high-speed memory devices. The latter series is for testing memory devices including flash memory and multi-chip packages at wafer sort and final test.
In such automated test equipment or testers, a plurality of test results might be obtained and stored at various locations remote from a central processing area. For example the results might be generated on the basis of different stimulus signals provided by a plurality of processing devices, or processors, which not only generate the stimulus signals, but also receive the response signals from the device under test or from a plurality of devices under test. For a test action, usually a test routine is executed on all channels in parallel. The test routines being executed or the data used by the test routines may differ between channels. However, for fast test execution it may be desired to make use of broadcast and common read wherever possible which necessitates that related test data of different channels is stored in all these channels at the same memory address. Finding out how to allocate memory chunks of certain sizes over certain sets of channels is done by the tester memory management. For some complex test applications there may be a constraint that related data of different channels has to be aligned at the same address which results in unused gaps in the tester memory. With increasing computing power of embedded processor inside the test processors each processor may manage its memory on its own and in the communication between the central processor and the test processors only symbolic addresses for memory chunks may be used. By this the constraint that related data of different channels has to be aligned at the same address may be avoided. However this may necessitate that the central processor knows the minimum or maximum of some values stored in the test processors. One example for this is the question: given a set of channels, how much memory can one still allocate over all these channels, i.e., what is the minimum size of the largest contiguous block of free memory on each of these channels?